FIELD OF THE INVENTION
The invention relates to a CMOS buffer circuit having a p-channel MOS transistor with a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source, and an n-channel MOS transistor being connected in series therewith and having a source terminal connected to the reference potential and a drain terminal connected to the output terminal.
As can be learned, for instance, from an article entitled "CMOS Output Buffers for Megabit DRAM's" in the IEEE Journal of Solid-State Circuits, Vol. 23, No. 3, June 1988, a major problem with such CMOS circuits is that they have great sensitivity with respect to the so-called latch-up phenomenon.
In that process a parasitic thyristor can be fired if the voltage at the output terminal is greater than the sum of the operating voltage and the base-to-emitter voltage of a transistor, or less than the difference between the reference potential and the base-to-emitter voltage of a transistor.
Since firing of the parasitic thyristor would cause destruction of the chip on which the CMOS circuit is located, suitable provisions for preventing latch-up must be found.
It is conventional to connect the substrate terminal of the n-channel MOS transistor to a voltage that is less than or equal to the reference potential, and to connect the substrate terminal of the p-channel MOS transistor to a voltage that is greater than the operating voltage. In normal operation, that can prevent latch-up from occurring.
However, since the two substrate voltages are derived from the operating voltage and are generated by so-called pump circuits, a certain amount of time passes before the voltages have attained their final value after the operating voltage is turned on. During that time, firing of the parasitic thyristor continues to be possible, if a corresponding level is present at the output terminal of a CMOS buffer circuit.